A steady increase in the number of transistors that can be built on a chip surface has gain importance in microelectronics during the past decades. The industry data show that the number of bits/chip will be increased from 1 kilobit (Kb) in the late 1960's to 1 Gigabit (Gb) by the end of the decade. It is recognized that device geometries both in the horizontal and in the vertical directions, must shrink steadily to allow such an increase in density to occur. One other benefit achieved by the scaling down of devices to smaller geometries is the increase in circuit speed. The smaller the minimum feature size, i.e., the minimum line-width or line-to-line separation that can be printed on the surface of a wafer, the larger the number of circuits can be placed on the chip resulting in a higher circuit speed.
One of the most frequently used processing techniques in microelectronics for fabricating integrated circuits (ICs) and very large scale ICs (VLSI) is lithography. The term lithography is used to describe a process in which a pattern is reproduced in a layer of material that is sensitive to photons, electrons or ions. The principle is similar to that used in photography in which an object is imaged on a photo-sensitive emulsion film. After development, the exposed regions of the film are left as a layer of metallic silver, while the unexposed regions are removed, resulting in a printed image of the object. While the final product is a printed image in photography, the image in microelectronics is typically an intermediate pattern which defines regions where material is to be etched or implanted.
The manufacturing process for IC devices is dependent upon the accurate reproduction of computer aided design (CAD) generated patterns onto the surface of a substrate. The replication process is typically performed by a lithographic technique, specifically an optical lithographic technique, that is preceded and followed by a variety of etching and ion implantation processes. Lithography is a critical step in semiconductor manufacturing because it is used repeatedly in a process sequence that depends on the device design. The lithographic process determines the device dimensions, which affect not only the quality but also its production volume and manufacturing cost. Lithography transforms complex circuit diagrams into patterns which are defined on the wafer in a succession of exposure and processing steps to form a number of superimposed layers of insulators, conductors and semiconductor materials. For instance, typically between 5 and 30 lithographic steps and several hundred processing steps between exposures are required to fabricate a semiconductor IC package.
A typical photolithographic process can be carried out on a wafer surface by the operating steps of first oxidizing the silicon surface to obtain a thin layer of silicon dioxide, then coating a layer of material that is sensitive to radiations such as ultraviolet light, electron beams or X-ray beams, then imprint a latent image on the material by a lithographic patterning technique, then amplify the latent image by an appropriate development method, the reserve areas delimiting the design to be reproduced on the silicon dioxide layer, then stabilize the image by an appropriate fixing method or a lithography method, and then plasma etching the silicon dioxide surface through openings obtained in the dioxide layer to obtain areas variously doped in the silicon dioxide subsequently defining two-dimensional geometric shapes on the surface of the substrate for the circuit, such as the gate electrodes, contacts, vias and metal interconnects.
Optical lithography, as commonly used in the manufacture of integrated circuits (ICs) and very large scale ICs (VLSI), involves a series of steps for obtaining complex etched structures on a wafer. An optical lithographic patterning process involves the illumination of a metallic coated quartz plate known as a photomask which contains a magnified image of the computer generated pattern etched into the metallic layer. An illuminated image is reduced in size and patterned onto a photosensitive film deposited on the device substrate. Each time the photolithographic steps are repeated, the accuracy of the process determines the quality and the yield of the IC fabrication process. The performance enhancement of advanced VLSI circuitry is increasingly limited by the lack of pattern fidelity in a series of lithographic and reactive ion etching (RIE) processes conducted at extremely small dimensions (e.g., in the sub-half-micron level). In a photolithographic process, a pattern is transferred from a photomask to a photosensitive film (i.e., a photoresist layer) on a wafer. In the RIE process, the pattern in the photoresist is in turn transferred into a variety of conductive or insulating films on the wafer substrate. A successful fabrication process for integrated circuits is therefore closely dependent upon a successful lithographic technique.
During each lithographic step, deviations may be introduced to distort the image that the photomask transfers to the wafer surface. For example, as a result of an optical interference and other interferences which occur during a pattern transfer, images formed on a wafer surface deviate from the original dimension and shape of the photomask that was stored in the computer. The deviations depend on the characteristics of the pattern as well as a variety of processing parameters. Since deviations significantly affect the performance of a semiconductor device, different techniques have been developed to focus on methods of compensation for the optical proximity effect so that they can be included in a CAD file to improve the image transfer process.
The pattern geometries used in fabricating IC devices are frequently of rectangular shape. When rectilinear geometries are printed on a wafer surface, problems are frequently observed at the corner regions of the pattern. For instance, when exposed to light or radiation, a photoresist integrates energy contributions from all surrounding areas. This means that the light intensity in one vicinity of the wafer is affected by the light intensity in neighboring vicinities. This phenomenon and, in general, distortions that affect dimensions and shapes of wafer features are referred to as proximity effects.
With the advancement in modern computer aided design technology, it is possible to predict the proximity effect and to modify a layout to offset the expected deviations. A selective biasing of mask patterns to compensate for pattern deviations occurring during wafer processing is therefore a desirable alternative to the costly development of new higher resolution processes. The term optical proximity correction (OPC) is therefore used to describe the process of selective biasing in mask patterns for compensating a proximity effect occurred in an optical image transfer process. The technique of biasing patterns to compensate for image transfer deviations has also been applied to E-beam lithography to counteract the effects of back scattered electrons. The techniques of OPC therefore enable the use of an automatic pattern biasing concept in pattern transfer processes in VLSI and ULSI technologies.
To implement an OPC process, a series of shrink and expand operations is employed to fracture a CAD pattern data base into basic rectangles abutting at vertices existing in the original design. The rectangles are then classified as to their functional relevance based on their spatial relationships to prior or subsequent CAD design levels. By shifting the edges of only the basic rectangles deemed relevant for the improvement of the VLSI device performance, the generation of new vertices is minimized and effort is expended only on high value added portions of the circuit design. For example, a plurality of gate regions in a CAD design is first identified. Then, a plurality of design shapes in the CAD design is sorted according to their geometric types. The plurality of sorted design shapes shares at least one side with a second design shape. The sorted design shapes are then grouped according to their widths. Finally, all of the grouped design shapes having been identified as gate regions are biased based on applicable OPC rules. FIGS. 1A and 1B show test patterns before and after OPC are printed on a plain wafer that does not have topography or other process-induced CD variations. It is possible to get a corrected pattern through theoretical aerial image correction on plain wafers by a commercial OPC software. However, the software would not work on wafers that have topography or other process-induced CD variations.
In practice, when a photomask is received from a customer and reproduced on a wafer surface, there are frequently critical dimension (CD) variations at various locations on the wafer surface caused by optical distortions. Conventionally, these CD variations are compensated by using commercially available software for computer aided design files. Another conventional method for compensating CD variations caused by distortions formed in optical imaging on a photoresist layer, i.e., sometimes known as a photoresist swing effect, is to add an anti-reflection coating layer prior to the coating of the photoresist layer. For instance, when a wafer surface has been processed to provide a thin gate oxide layer and thick field oxide regions, and a polysilicon layer is subsequently deposited thereon, an anti-reflection layer (i.e., a bottom anti-reflective coating (BARC) layer) can be first coated to cover the polysilicon layer. A photoresist layer is then coated on top of the BARC layer. Since the swing effect is caused by the reflectance of incident light beams on a wafer surface and the formation of constructive and destructive interferences, the additional layer of BARC substantially eliminates light reflectance from the wafer surface by absorbing lights and thus minimizing a photoresist swing effect. Substantially smaller CD variations on the surface of the wafer can be achieved by the BARC addition.
Additional problem that causes proximity effect on the surface of a wafer is the topography of the wafer surface formed after the deposition of a polysilicon and an anti-reflectance coating layer. Topography exists even after a planarization process has been conducted on the wafer surface. For instance, when a polysilicon conducting line is formed on a wafer surface which has a thin oxide coating layer at certain sections and thick field oxide layers at other sections, the width of the conducting line formed at different locations, i.e., on top of the thin oxide region or the thick field oxide regions, are different. The reason for the variation in the width of the polysilicon line formed is the variations in the thicknesses of the photoresist layer coated. This is shown in FIG. 2.
It is seen in FIG. 2 that when substrate 26 is formed with a thin oxide layer 28 and thick field oxide regions 30 on top, the polysilicon layer 34 deposited conforms to the topography of the oxide layers. The topography of the polysilicon layer 34 is then reproduced in a BARC layer 36 subsequently deposited on top of the polysilicon layer for reducing a swing effect on the photoresist layer. However, as seen in FIG. 2, the photoresist layer 42 subsequently coated on top of the BARC layer 36 has significant thickness variations. For instance, the photoresist layer 42 at section 44 is substantially thicker than at section 46. It is known that during a photoresist imaging process, the photoresist layer is subjected to the same exposure dose of either an optical source or an electron-beam source. Consequently, the energy dosage requirement between sections 46 and 44 is different due to the different resist thickness. As a result, the latter needs lesser exposure dosage than the former. This creates a CD variation on the polysilicon line formed from the polysilicon layer 34.
Even though the utilization of a bottom anti-reflective coating layer reduces a photoresist swing effect, the CD variations on the feature formed (i.e., the line) still exist. Moreover, the anti-reflective coating layer is frequently coated of an organic material which has approximately the same etch rate as an organic photoresist layer during a photoresist etching process. It is therefore necessary, when the substrate must be etched all the way through so that its surface can be exposed, to first etch away the BARC layer before the polysilicon layer can be etched. The utilization of a BARC layer therefore creates process complications for a semiconductor fabrication process. First, the additional cost of a BARC layer and the processing time required for coating such layer contribute to the total fabrication costs. Secondly, the etching process for the polysilicon layer becomes more complicated since the process must also etch away the BARC layer. Thirdly, the thickness of the photoresist layer deposited on top of the wafer surface can not be reduced in order for the photoresist to function satisfactory. It is known that the resolution achieved in a photolithographic process is inversely proportional to the thickness of the photoresist layer. Therefore, the thicker photoresist layer required in a photolithographic process produces a less than satisfactory resolution.
It is therefore an object of the present invention to provide a method for proximity correction on a wafer surface during a photolithographic process that does not have the drawbacks and shortcomings of the conventional proximity correction methods.
It is another object of the present invention to provide a method for interlayer proximity correction on a wafer surface that eliminates the need for an anti-reflective coating layer.
It is a further object of the present invention to provide an interlayer method for proximity correction on a wafer surface during a photolithographic process by first correcting optically induced proximity effect and then correcting process-induced proximity effect.
It is another further object of the present invention to provide an interlayer method for proximity correction on a wafer surface during a photolithographic process by first conducting an optical proximity correction and then performing a photomasking process to measure the CD variations on a wafer surface and to feedback the variations to a computer aided design file for correcting the process-induced proximity effect.
It is still another object of the present invention to provide an interlayer method for proximity correction on a wafer surface during a photolithographic process which is capable of correcting process-induced proximity effect such as line-end shortening and photoresist swing effect.
It is yet another object of the present invention to provide a method for proximity correction on a wafer surface during a photolithographic process that can be used effectively to correct proximity effect caused by topography on the wafer surface.
It is still another further object of the present invention to provide an interlayer method for proximity correction on a wafer surface during a photolithographic process in which the proximity effect existed between a polysilicon layer and an underlying oxide layer can be effectively corrected.